Non-x86 Processors
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PROCESSORs: Manufacturer:
Alpha 21164A DEC (Digital Equipment Corporation)
HP 9000 Hewlett Packard
HP PA-8000 Hewlett Packard
MC 68000 Motorola
PowerPC 601 Motorola
PowerPC 603 Motorola
PowerPC 604 Motorola
PowerPC 620 Motorola
R10000 MIPS
RS/6000 IBM
UltraSparc I SUN Microsystems / Microelectronics
UltraSparc II SUN Microsystems / Microelectronics
SuperSparc I SUN Microsystems / Microelectronics
SuperSparc II SUN Microsystems / Microelectronics
PROCESSOR Manufacturer:





MC 68000
32 bit processor manufactured by the
Motorola. In the early eighties this processor allowed the Apple corporation to bring out the worlds first home computer system to use a graphical user interface (GUI). With some 16 registers and linear address space (addressing 16MB directly) it was a pleasure to do assembly programming with this unit. The large number of registers meant that even in an enviroment such as the Macintosh operating system that between three and six data registers and three to six address registers would still be available for end user applications.
The first family member used an external 24 bit address bus and 16 bit data bus. The family also features provision for co-processors and fourteen addressing modes. A wide range of variants has been produced from micro-controlers to high end units satisfying various packaging and energy requirements. (more info)


PowerPC 601
The PowerPC 601 microprocessor is the first 32-bit implementation of the PowerPC (TM) Reduced Instruction Set Computer (RISC) architecture. The PowerPC 601 microprocessor provides high levels of performance for desktop, workstation, and symmetric multiprocessing computer systems and offers design flexibility through operation at either 2.5 volts (601v) or 3.6 volts (601).
The PowerPC 601 microprocessor is a superscalar design capable of issuing and retiring three instructions per clock. Instructions issue to multiple execution units, execute in parallel, and can complete out of order, while preserving program correctness. The PowerPC 601 integrates three execution units-an integer unit (IU), a branch processing unit (BPU), and a floating-point unit (FPU). It also incorporates a memory management unit (MMU), a unified instruction and data cache, a real-time clock (RTC), and on-chip test capability.

PowerPC 603
he PowerPC 603 microprocessors are a low-power implementation of the PowerPC (TM) reduced instruction set computer (RISC) architecture. The PowerPC 603 microprocessors offer workstation-level performance packed into a low-power, low-cost design ideal for desktop computers, notebooks, and battery-powered systems, as well as embedded applications. The PowerPC 603 microprocessors feature three power-saving modes: doze, nap and sleep. These user-programmable modes progressively reduce the power drawn by the processor. The PowerPC 603 microprocessor has separate 8-Kbyte, physically-addressed instruction and data caches. Both caches are two-way set-associative. Power consumption at Full Operation is 3 watts maximum at 80 MHz. The PowerPC 603e microprocessor has separate 16-Kbyte, physically-addressed instruction and data caches. Both caches are four-way set-associative. Power consumption at Full operation is 3.5 watts maximum at 100 MHz. The PowerPC 603e-200 microprocessor is a low-power 200 MHz implementation of the PowerPC(TM) Reduced Instruction Set Computer (RISC) architecture. The PowerPC 603e-200 microprocessor features a low-power 2.5-volt design. The PowerPC 603e-240 microprocessor is a low-power 240 MHz implementation of the PowerPC(TM) Reduced Instruction Set Computer (RISC) architecture. The PowerPC 603e-240 microprocessor features a low-power 2.5-volt design.


PowerPC 604
The PowerPC 604 microprocessor family is a 32-bit implementation of the PowerPC(TM) reduced instruction set computer (RISC) architecture. The PowerPC 604 family of microprocessors provides high levels of performance for desktop, workstation, and symmetric multiprocessing computer systems and is software- and bus-compatible with the PowerPC 603(TM) and PowerPC 601(TM) microprocessor families. The PowerPC 604 operates at 133, 120, and 100 MHz while the PowerPC 604e operates at 200, 180, and 166 MHz. The PowerPC 604e microprocessor offers significant performance improvements over the original. The increased performance is realized through microprocessor design enhancements - including doubling of caches and through aggressive use of the latest manufacturing technology processes. It is also significantly smaller and uses less power through implementation of nap and doze power-saving modes. Both are superscalar designs capable of issuing four instructions per clock cycle to six independent execution units. The PowerPC 604 microprocessor family uses dynamic branch prediction to improve the accuracy of instruction prefetching. Dynamic branch prediction and the ability to speculatively execute through two unresolved branches minimize pipeline stalls and allow the multiple execution units to provide a high level of efficiency and throughput. Although the PowerPC 604 microprocessor supports out-of-order execution, in-order instruction completion guarantees precise exceptions.


PowerPC 620
The PowerPC 620 microprocessor is a 64-bit implementation of the PowerPC(TM) Reduced Instruction Set Computer (RISC) architecture. The PowerPC 620 microprocessor provides high levels of performance for technical and scientific work stations, application and LAN servers and symmetric multiprocessing computer systems and is software compatible with the PowerPC 601(TM), PowerPC 603(TM), and PowerPC 604(TM) microprocessors.
The PowerPC 620 microprocessor is a superscalar design capable of issuing four instructions per clock cycle to six independent execution units. The PowerPC 620 microprocessor uses dynamic branch prediction to improve the accuracy of instruction prefetching. Dynamic branch prediction, combined with the ability to speculatively execute through four unresolved branches, minimizes pipeline stalls and allows the multiple execution units to provide a high level of efficiency and throughput. The PowerPC 620 microprocessor supports out-of-order execution with in-order instruction completion assuring precise exceptions.


R10000
The R10000 processor is a single-chip superscalar RISC microprocessor that is a follow-on to the MIPS RISC processor family that includes, chronologically, the R2000, R3000, R6000, R4400, and R8000.
The R10000 processor uses the MIPS ANDES architecture, or Architecture with Non-sequential Dynamic Execution Scheduling.
The R10000 processor has the following major features:



UltraSPARC I
STP1030ABGA, 167MHz & 200MHz RISC Microprocessor. UltraSPARC is the newest and most powerful member of the SPARC family of microprocessors. With its 64-bit, superscalar architecture, UltraSPARC is one of the fastest microprocessors on earth. It is also the industry's first processor with on-chip multimedia support, including real-time MPEG-2 decompression. For these and many other reasons, UltraSPARC is the engine of choice for enterprise network processing.

UltraSPARC II
STP1031LGA, 250MHz RISC Microprocessor. UltraSPARC-II is a second generation product of the UltraSPARC family of pipeline based products. In addition to using a new process technology, UltraSPARC-II provides a higher clock frequency, multiple SRAM modes and system to processor clock ratios. These accommodate multiple price points for system developers, and at the same time, provide software compatibility with existing UltraSPARC-I based systems.

SuperSPARC I
Highly Integrated 32-Bit RISC Microprocessor. The STP1020A is a new member of the SuperSPARC family of microprocessor products. Like its predecessors (STP1020N and STP1020) this new part is fully SPARC version 8 compliant and is completely upward compatible with the earlier SPARC version 7 implementations running over 8500 SPARC applications and development tools.

SuperSPARC II
Highly Integrated 32-Bit RISC Microprocessor. The STP1021 is a new member of the SuperSPARC family of microprocessor products. Like its predecessors (STP1020N and STP1020A) this new part is fully SPARC version 8 compliant and is completely upward compatible with the earlier SPARC version 7 implementations running over 8500 SPARC applications and development tools.

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